Crossbar structure with input-position dependent repeater structure

ABSTRACT

A crossbar circuit ( 30, 40, 50, 60, 70, 80, 90, 100 ) having programmable repeater structures adapted to allow configuration of the crossbar with inputs at multiple sides of the crossbar die. A plurality of repeaters ( 62 ) are arranged in different repeater structures such that the repeater arrangement can be connected to inputs at different locations as a function of the corresponding input as it is physically positioned around the periphery of the crossbar. A pseudo code is provided allowing the repeater structures to be custom configured to corresponding inputs as a function of the desired crossbar as it is designed to be utilized in a particular large integrated circuit, such as a VLSI chip.

FIELD OF THE INVENTION

[0001] The present invention is generally related to crossbar circuits,and more particularly to large crossbar circuits utilized in largeintegrated circuits such as VLSI chips.

BACKGROUND OF THE INVENTION

[0002] Crossbars are structures which can connect any input to anyoutput. It is common in VLSI chips to implement large crossbars, such asshown at 10 in FIG. 1, to switch inputs coupled to one circuit block 12to outputs feeding a second circuit block 14. For example, a crossbarmay have 64 inputs and 64 outputs, where each of the inputs and outputsis 16 bits wide. The crossbar is built largely out of multiplexers,where each output is driven by a 16 bit wide, 64 input multiplexer. The64 input mux is in practice implemented as a tree of smaller muxes. With64 crossbar outputs, there are 64 instances of this 64-input, 16 bitwide mux.

[0003] Crossbars conventionally can be efficiently implemented asregular datapath structures, where each output mux is a bitstack, or aregular datapath component. The 64 output muxes are then placed in asequence. For example, as shown at 16 in FIG. 2, the mux bitstacks arehorizontal, with bit 0 on the left and bit 15 on the right. The datapathis then built up vertically, with output mux 0 on the bottom and outputmux 63 on the top.

[0004] In this arrangement, each of the 64 16 bit input wires must bebroadcast to all 64 output muxes. FIG. 3 shows these 1024 wires at 18running vertically the entire height of the crossbar 10. It is typicallythe case that the load represented by the inputs of the 64 muxes is toolarge to be driven by a single wire, where the wire 18 is long enoughthat the resulting RC time constant is unacceptable. As a result,repeaters 20 must be inserted in the input wires 18, as shown in FIG. 4for the case of an input wire divided into 4 segments by 3 repeaters.

[0005] It is often the case that the data input wires 18 are registeredjust as they come into the crossbar 10. The output data wires 18 mayalso be registered by registers 22, as shown in FIG. 5, giving a fullclock cycle for the crossbar to function, and allowing time for theinput and output signals on the wires 18 to travel potentially longdistances. When the data inputs are registered, the repeaters 20 aredriven from the buffered output of the registers.

[0006] The arrangement of FIG. 5 is a conventional case where all 1024data input wires are input to the bottom of the crossbar module. It isalso possible to input wires to the top of the module, as shown in FIG.6, using repeaters to form a basic repeater structure as shown.

[0007] There is desired an improved crossbar adapted to have data inputsat multiple sides of the module periphery and an architecture whichprovides custom programming to achieve such a feature.

SUMMARY OF THE INVENTION

[0008] The present invention achieves technical advantages as a crossbarcircuit having a plurality of repeaters forming different repeaterarrangements, whereby inputs to the crossbar circuit are defined about aperimeter of the circuit, with each input coupled to one repeaterarrangement and being configured as a function of the input locationrelative to the crossbar circuit on the die.

[0009] The repeater topology is dependent upon the physical location ofthe repeater structure in the crossbar, which location is a function ofthe input locations to be interconnected thereto. This advantageouslyallows a plurality of muxes to be driven by the repeaters, with thecrossbar circuit outputs being provided by these muxes. Preferably, themuxes are petitioned into mux groups, wherein each mux group is drivenby repeaters positioned proximate to the respective group. Each inputpreferably has the plurality of bits, wherein the repeater arrangementis provided for each bit.

[0010] The various repeater arrangements comprise serially connectedrepeaters, and a data register associated with each repeater arrangementmay feed the repeater arrangements at different sections thereof. Forinstance, one data register may feed the end of the repeater structure,while other data registers feed the midsection of the repeaterarrangements, depending upon where the input to the respective dataregister is located relative to the die periphery.

[0011] The data register/repeater arrangements are adapted to beprogrammed by a pseudo code and executed by a layout compiler, such thatinputs are selectively coupled to the repeater arrangements as afunction of the relative position of the input at the crossbarperiphery. Advantageously, the inputs can be selectively arranged aboutthe perimeter of the crossbar die such that the crossbar can be customconfigured to interface to other circuit blocks designed thereabout fora particular design.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a block diagram of an ASIC circuit including a largecrossbar interfacing various circuits blocks interfaced at differentsides of the crossbar circuit;

[0013]FIG. 2 is a block diagram of a crossbar circuit with mux bitstacks arranged horizontally;

[0014]FIG. 3 is a block diagram of a crossbar illustrating the pluralityof vertically oriented wires extending from corresponding inputs to eachof the muxes;

[0015]FIG. 4 is a block diagram of a repeater structure for one inputadapted to feed different groups of muxes;

[0016]FIG. 5 is a block diagram of a crossbar having all inputs providedat the bottom of the crossbar module and feeding a respective dataregister and repeater arrangement;

[0017]FIG. 6 is a block diagram of a crossbar with all inputs receivedat the top of the module;

[0018]FIG. 7 is a block diagram of a crossbar having differenttopologies of repeater arrangements, the different topologies being afunction of where the associated input is located about the periphery ofthe module;

[0019]FIG. 8 is a block diagram of a crossbar module with inputs beingprovided at both the lower portion and the top portion of the crossbarmodule;

[0020]FIG. 9 is a crossbar depicting some of the inputs coming from theside of the crossbar and connected to different repeater arrangementsbeing a function of the vertical location of the input;

[0021]FIG. 10 is an illustration of a crossbar having inputs defined atall four sides of the crossbar module, depicting some of the inputsalong one side feeding the respective repeater arrangement;

[0022]FIG. 11 depicts a crossbar with inputs alternating between theleft side and the right side of the crossbar module;

[0023]FIG. 12 illustrates a crossbar with inputs alternating from theleft side to the right side in a serpentine pattern;

[0024]FIG. 13 depicts a crossbar with inputs alternating from the leftside to the right side in groups of four; and

[0025]FIG. 14 depicts a crossbar with inputs serpentining from left toright in groups of four.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0026] The present invention derives technical advantages as a crossbaraccommodating inputs from many sides to interconnect large circuitsdefined about the periphery of the crossbar. Depending on where the datainputs come from, the arrangement of repeaters in the crossbar isdifferent, as shown at 30 and 40 in FIGS. 7-8. For the example of a64×64×16 bit crossbar, it is usually desirable to have the 1024 datainput wires come from multiple sides of the crossbar module periphery.FIG. 8 shows a crossbar 40 having some inputs coming from the bottom andsome from the top of the crossbar module. Note that on the bottom,inputs 0-31 arrive, with the 32 vertically extending wires for bit 0 onthe left, and then 32 wires for each successive bit until finally the 32input wires for bit 15 lie on the right. Likewise, for the top, whereinputs 32-63 arrive, bit 0 is on the left and bit 15 is on the rightwith downwardly extending wires. Each of these wires includes repeaters42 forming a repeater topology as a function of the input location aswill now be discussed further.

[0027]FIG. 9 shows a crossbar arrangement at 50 where some inputs aredefined at the left side of the crossbar. The 16 bits of input 12 arrivein sequence, following which are the 16 input bits of the next input.Further up the left side of the crossbar, the 16 bits of input 27 areshown arriving in sequence. The relative location of the input relativeto the crossbar determines the associated repeater structure topology,as shown.

[0028] It is desired to be able to conveniently generate customcrossbars, and the desired port locations of the data input signalsrelative to the crossbar periphery must be accommodated, since eachcrossbar application requires inputs to come from distinctly differentlocations. Different input locations result in different repeaterstructures. An algorithm to produce and connect these repeaterstructures to inputs will now be described, as well as the resultingstructures themselves, followed by examples in view of FIG. 10 and FIG.11.

[0029] Compiler Algorithm

[0030] First, for a particular crossbar design, the number of segmentsthe data input wires will be broken into is determined, identified asNseg. There will be Nseg repeater buffers 62 driving each wire, whereone of the wire segments is driven directly by a buffer off the datainput register 22, and the other segments are driven from otherrespective repeaters 62. The output muxes are divided into Nseg groups,each mux being fed from a different repeater output of a data inputwire. For the case of a crossbar with 64 inputs and Nseg=4, the inputwire is broken into 4 segments, with 16 adjacent output muxes being fedfrom each repeater output.

[0031] In this algorithm, the signal naming of the 4 repeated versionsof a data input signal is as follows:

[0032] dinbuf[inpsig] [repeat]<bit>

[0033] where “inpsig” ranges from 0 to 63 for the 64 data inputs,“repeat” ranges from 0 to 3 for the 4 segments of the buffered datainput wire, and “bit” ranges from 0 to 15.

[0034] The index repeat corresponds to the physical location of the datainput wire segment, from 0 on the bottom to 3 on the top. Namely:

[0035] The bottom 16 output muxes 0 to 15 are fed from the wires:

[0036] dinbuf[inpsig] [0]<bit>,

[0037] the next adjacent 16 output muxes 16-31 are fed from the wires:

[0038] dinbuf[inpsig] [1]<bit>,

[0039] the next adjacent 16 output muxes 32-47 are fed from the wires:

[0040] dinbuf[inpsig] [2]<bit>,

[0041] and the last adjacent 16 output muxes 48-63 are fed from thewires:

[0042] dinbuf[inpsig][3]<bit>.

[0043] This arrangement is independent of the positioning of the datainput ports. However, according to the present invention, the topologyof the repeaters is dependent on the physical location of the inputports. Let “input segment” be a function which given the data inputnumber, returns which segment the data input lies in. This function canbe designed custom for each crossbar application to indicate desiredport locations, allowing flexibility in design. In this example, inputsat the bottom of the crossbar return 0, inputs at the top of thecrossbar return 3, and other inputs along the left or right sides of thecrossbar return from 0 to 3, depending on which 25% of the crossbarheight they fell upon.

[0044] The following pseudo code generates all 4 repeaters in thesequence:

[0045] for data_input from 0 to 63//loop over 64 16b data input wiresinput_loc

input_segment(data_input);//which segment the input falls into

[0046] for bit from 0 to 15//loop over the 16 bits

[0047] //this is the first input buffer,

[0048] //located wherever the input is,

[0049] //buffering the input data registerdinbuf[data_input][input_loc]<bit>

buffer(din_q[data_input]<bit>);

[0050] for buffer_num from 1 to 3//loop over the remaining 3 repeatersinput_is_above

(input_loc>=buffer_num);

[0051] inpsig

if input_is_above then buffer_num else (buffer_num −1);

[0052] outsig

if input_is_above then (buffer_num −1) else buffer_num;

[0053] //these are the next 3 repeater buffers, at the 25, 50 and 75%locations.

[0054] dinbuf[data_input][outsig]<bit><

buffer(dinbuf[data_input][inpsig]<bit>);

[0055] end;

[0056] end;

[0057] end;

[0058] Expanding the cases:

[0059] inp@0 0->1->2->3

[0060] inp@1 0<-1->2->3

[0061] inp@2 0<-1<-2->3

[0062] inp@3 0<-1<-2<-3

[0063] Each arrow in the line represents one repeater out of the final 3repeaters in the sequence, located at the 25%, 50% and 75% portionsalong the vertical extent of the crossbar module. If the input is belowrepeater 1 at the 25% point, repeater 1 takes dinbuf[inpsig][0] andproduces dinbuf[inpsig][1], i.e., 0->1. If the input is above repeater 1at the 25% point, repeater 1 takes dinbuf[inpsig][1]and producesdinbuf[inpsig] [0], i.e., 1->0.

[0064] Notice that the first buffer, driven from the registered datainput, has a repeat index corresponding to its physical location, so foran input arriving in segment 2, the buffers would produce signals:

[0065] dinbuf[data_input] [2]<bit>.

EXAMPLES

[0066] As a first example shown in FIG. 10, a crossbar 60 will bediscussed which has 64 inputs and 64 outputs, each 16 bits wide. The 64inputs are distributed to all 4 sides of the crossbar module periphery,with 16 inputs per side. Inputs 0-15 come from the bottom, inputs 16-31come from the right side, inputs 32-47 come from the top and inputs48-63 come from the left side.

[0067] For bottom inputs 0-15, the 16 bit 0 inputs are on the left,followed by the 16 bit 1 inputs, until finally the 16 bit 15 inputs areon the right. The same is true of the top inputs 32-47.

[0068] For right side inputs 16-31, all 16 bits of each input areconsecutively arranged, with all bits of input 16 starting at the bottomof the right side, followed by all bits of input 17, progressing untilfinally all bits of inputs 31 are at the top of the right side. The leftside inputs 48-63 are similarly arranged, with input 63 at the bottom ofthe left side and input 48 at the top of the left side.

[0069] In this example, each of the vertical data input wires areseparated into 4 segments, each separated from the next by a repeater62. In order to customize the crossbar compiler to this floorplan, it ismerely necessary to produce a function input_segment, which for eachdata input, returns which input segment the data falls into. Thefollowing piece of pseudo code provides the desired function:

[0070] function input_segment(input_num) { if (0 <=input_num <= 15) 0elseif (16 <= input_Num <= 31) (logand 3 (input_num >> 2)) //bits <3:2>elseif (32 <= input_num <= 47) 3 else           (logand 3 (logxor 3(input_num >> 2))) endif; }

[0071] Inputs 0-15 on the bottom belong to segment 0, while inputs 32-47on the top belong to segment 3. Inputs 16-31 on the right side aredistributed among the four segments, with four consecutive inputs toeach segment. Thus:

[0072] inputs 16-19 belong to segment 0

[0073] inputs 20-23 belong to segment 1

[0074] inputs 24-27 belong to segment 2

[0075] inputs 28-31 belong to segment 3.

[0076] Inputs 48-63 on the left are distributed among the four segments,with four consecutive inputs to each segment. Thus,

[0077] inputs 48-51 belong to segment 3

[0078] inputs 52-55 belong to segment 2

[0079] inputs 56-59 belong to segment 1

[0080] inputs 60-63 belong to segment 0.

[0081] As a second example, a crossbar 70 is shown in FIG. 11, againwith 64 inputs and 64 outputs, each 16 bits wide. The data input wiresare again separated into 4 segments. This time, the data inputs will allcome from the left and right sides of the crossbar, alternating sides,starting from the bottom.

[0082] In this case, the function input_segment is simpler, because themapping is simple;

[0083] inputs 0-15 belong to segment 0

[0084] inputs 16-31 belong to segment 1

[0085] inputs 32-47 belong to segment 2

[0086] inputs 48-63 belong to segment 3.

[0087] function input_segment(input_num) { (logand 3 (input_num >> 4))   //bits <5:4> }

[0088] Bits <5:4>of the input num determine the input section.

[0089] It should be noted that it doesn't matter whether inputs are onthe left or right, so the fact that in the above example the inputsalternate from the left to right side is unimportant. Many differentleft-right patterns would have the same input_segment function.

[0090]FIG. 12 shows a crossbar 80 with the inputs alternating from leftto right in a serpentine pattern.

[0091]FIG. 13 shows a crossbar 90 with the inputs alternating from leftto right in groups of 4 signals; first 4 on the left, then 4 on theright, etc.

[0092]FIG. 14 shows a crossbar 100 with the inputs serpentining fromleft to right, in groups of 4 signals; where they are on the left, thenright, right, left sides. All of these data input pin location patternsin FIGS. 12-14 share the same input_segment function above.

[0093] In summary, the algorithm for defining the crossbar configurationis as follows:

[0094] Let there be N output muxes.

[0095] Let there be Nseg segments in the data input wires, withrepeaters between them, so that each wire drives N/Nseg output muxes.

[0096] Divide the output muxes into Nseg groups of physically adjacentmuxes, numbered from 0 to Nseg-1.

[0097] Then, muxes in group K from 0 to Nseg-1 are driven by data inputwire segment K.

[0098] Let input_segment be which one of the Nseg groups a data inputwire port physically lies in.

[0099] Let the registered data input be called din_q.

[0100] Then, the first buffer takes din_q as its input and producesdinbuf[input_segment] as its output.

[0101] For the remaining Nseg-1 buffers, for buffer number M from 1 toNseg-1, if input_segment>=M, then buffer M takes dinbuf[M] as its inputand produces dinbuf[M-1] as its output.

[0102] For the remaining Nseg-1 buffers, for buffer number M from 1 toNseg-1, if input segment <M, then buffer M takes dinbuf[M-1] as itsinput and produces dinbuf[M] as its output.

[0103] Though the invention has been described with respect to aspecific preferred embodiment, many variations and modifications willbecome apparent to those skilled in the art upon reading the presentapplication. It is therefore the intention that the appended claims beinterpreted as broadly as possible in view of the prior art to includeall such variations and modifications.

We claim:
 1. A circuit, comprising; a crossbar; a plurality of repeatersforming a repeater arrangement, and forming different said repeaterarrangements; and a plurality of inputs, said inputs being defined abouta perimeter of said crossbar, wherein each said input is coupled to onesaid repeater arrangement being configured as a function of said inputlocation relative to said crossbar.
 2. The crossbar circuit as specifiedin claim 1 wherein said repeaters are arranged in a topology that isdependent upon the physical location of the input on the crossbar. 3.The crossbar circuit as specified in claim 1 further comprising aplurality of muxes being driven by said repeaters, said crossbar circuithaving outputs provided by said muxes.
 4. The crossbar circuit asspecified in claim 3 wherein the muxes are partitioned into groups, eachsaid group being driven by said repeaters positioned proximate saidgroup.
 5. The crossbar circuit as specified in claim 3 wherein each saidinput has a plurality of bits.
 6. The crossbar circuit as specified inclaim 5 wherein one said repeater arrangement is provided for each saidbit.
 7. The crossbar circuit as specified in claim 1 wherein some saidrepeater arrangements comprise serially connected said repeaters withsaid corresponding input feeding a midsection of said serially connectedrepeaters.
 8. The crossbar circuit as specified in claim 1 wherein saidrepeater arrangements are adapted to be programmed by a layout compilerpseudo code such that said inputs are selectively coupled to repeaterarrangements.
 9. The crossbar circuit as specified in claim 1 whereinsaid crossbar has multiple sides, wherein said inputs are configured atall said sides and selectively coupled to said repeater arrangements.10. The crossbar circuit as specified in claim 9 wherein said crossbarhas laterally extending muxes, wherein some said inputs of opposing saidcrossbar sides are coupled to a midsection of said associated repeaterarrangement at a node, such that said associated repeater arrangement iscoupled to said muxes located above and below said node.
 11. Thecrossbar circuit as specified in claim 9 wherein said inputs arearranged sequentially about a perimeter of said crossbar.
 12. Thecrossbar circuit as specified in claim 9 wherein said inputs arearranged in a zig-zag pattern between two said crossbar sides.
 13. Thecrossbar circuit as specified in claim 9 wherein said inputs arearranged in a serpentine arrangement between two said crossbar sides.14. The crossbar circuit as specified in claim 9 wherein said inputs arearranged in a modulo x zigzag pattern between two said crossbar sides,where x is a number greater than
 1. 15. The crossbar circuit asspecified in claim 9 wherein said inputs are arranged in a modulo xserpentine pattern between two said crossbar sides, where x is a numbergreater than
 1. 16. The crossbar circuit as specified in claim 5 whereinthere are N said repeaters per repeater arrangement, and N groups ofsaid muxes, wherein one said repeater arrangement associated with eachsaid bit is coupled to a corresponding group of muxes, N being a numbergreater than
 1. 17. The crossbar circuit as specified in claim 1 furthercomprising data registers coupled to the repeaters in a topology that isdependent upon the physical location of the data register on thecrossbar.
 18. The crossbar circuit as specified in claim 1 wherein saidcross bar circuit can be programmed in a plurality of configurations asa function of said inputs to be configured for use.
 19. The crossbarcircuit as specified in claim 17 wherein some said data registers feed amidsection of said repeater arrangements.
 20. The crossbar circuit asspecified in claim 1 further comprising data registers receiving theinputs and being coupled to said repeaters in a topology that isdependent on the physical location of the input coupled to the dataregister.